COMPUTER ORGANIZATION AND DESIGN
The Hardware/Software Interface
ARM
Edition
Chapter 2
Instructions: Language
of the Computer
Chapter 2 — Instructions: Language of the Computer — 2
Instruction Set
n The repertoire of instructions of a
computer
n Different computers have different
instruction sets
n But with many aspects in common
n Early computers had very simple
instruction sets
n Simplified implementation
n Many modern computers also have simple
instruction sets
§2.1 Introduction
Chapter 2 — Instructions: Language of the Computer — 3
The ARMv8 Instruction Set
n A subset, called LEGv8, used as the example
throughout the book
n Commercialized by ARM Holdings
(www.arm.com)
n Large share of embedded core market
n Applications in consumer electronics, network/storage
equipment, cameras, printers, …
n Typical of many modern ISAs
n See ARM Reference Data tear-out card
Chapter 2 — Instructions: Language of the Computer — 4
Arithmetic Operations
n Add and subtract, three operands
n Two sources and one destination
ADD a, b, c // a gets b + c
n All arithmetic operations have this form
n Design Principle 1: Simplicity favours
regularity
n Regularity makes implementation simpler
n Simplicity enables higher performance at
lower cost
§2.2 Operations of the Computer Hardware
Chapter 2 — Instructions: Language of the Computer — 5
Arithmetic Example
n C code:
f = (g + h) - (i + j);
n Compiled LEGv8 code:
ADD t0, g, h // temp t0 = g + h
ADD t1, i, j // temp t1 = i + j
SUB f, t0, t1 // f = t0 - t1
Chapter 2 — Instructions: Language of the Computer — 6
Register Operands
n Arithmetic instructions use register
operands
n LEGv8 has a 32 × 64-bit register file
n Use for frequently accessed data
n 64-bit data is called a “doubleword”
n 31 x 64-bit general purpose registers X0 to X30
n 32-bit data called a “word”
n 31 x 32-bit general purpose sub-registers W0 to W30
n Design Principle 2: Smaller is faster
n c.f. main memory: millions of locations
§2.3 Operands of the Computer Hardware
LEGv8 Registers
n X0 – X7: procedure arguments/results
n X8: indirect result location register
n X9 – X15: temporaries
n X16 – X17 (IP0 – IP1): may be used by linker as a
scratch register, other times as temporary register
n X18: platform register for platform independent code;
otherwise a temporary register
n X19 – X27: saved
n X28 (SP): stack pointer
n X29 (FP): frame pointer
n X30 (LR): link register (return address)
n XZR (register 31): the constant value 0
Chapter 2 — Instructions: Language of the Computer — 7
Chapter 2 — Instructions: Language of the Computer — 8
Register Operand Example
n C code:
f = (g + h) - (i + j);
n f, …, j in X19, X20, …, X23
n Compiled LEGv8 code:
ADD X9, X20, X21
ADD X10, X22, X23
SUB X19, X9, X10
Chapter 2 — Instructions: Language of the Computer — 9
Memory Operands
n Main memory used for composite data
n Arrays, structures, dynamic data
n To apply arithmetic operations
n Load values from memory into registers
n Store result from register to memory
n Memory is byte addressed
n Each address identifies an 8-bit byte
n LEGv8 does not require words to be aligned in
memory, except for instructions and the stack
Chapter 2 — Instructions: Language of the Computer — 10
Memory Operand Example
n C code:
A[12] = h + A[8];
n h in X21, base address of A in X22
n Compiled LEGv8 code:
n Index 8 requires offset of 64
LDUR X9,[X22,#64] // U for “unscaled”
ADD X9,X21,X9
STUR X9,[X22,#96]
Chapter 2 — Instructions: Language of the Computer — 11
Registers vs. Memory
n Registers are faster to access than
memory
n Operating on memory data requires loads
and stores
n More instructions to be executed
n Compiler must use registers for variables
as much as possible
n Only spill to memory for less frequently used
variables
n Register optimization is important!
Chapter 2 — Instructions: Language of the Computer — 12
Immediate Operands
n Constant data specified in an instruction
ADDI X22, X22, #4
n Design Principle 3: Make the common
case fast
n Small constants are common
n Immediate operand avoids a load instruction
Chapter 2 — Instructions: Language of the Computer — 13
Unsigned Binary Integers
n Given an n-bit number
0
0
1
1
2n
2n
1n
1n
2x2x2x2xx ++++=
-
-
-
-
!
n Range: 0 to +2
n
– 1
n Example
n 0000 0000 0000 0000 0000 0000 0000 1011
2
= 0 + … + 1×2
3
+ 0×2
2
+1×2
1
+1×2
0
= 0 + … + 8 + 0 + 2 + 1 = 11
10
n Using 32 bits
n 0 to +4,294,967,295
§2.4 Signed and Unsigned Numbers
Chapter 2 — Instructions: Language of the Computer — 14
2s-Complement Signed Integers
n Given an n-bit number
0
0
1
1
2n
2n
1n
1n
2x2x2x2xx ++++-=
-
-
-
-
!
n Range: –2
n – 1
to +2
n – 1
– 1
n Example
n 1111 1111 1111 1111 1111 1111 1111 1100
2
= –1×2
31
+ 1×2
30
+ … + 1×2
2
+0×2
1
+0×2
0
= –2,147,483,648 + 2,147,483,644 = –4
10
n Using 32 bits
n –2,147,483,648 to +2,147,483,647
Chapter 2 — Instructions: Language of the Computer — 15
2s-Complement Signed Integers
n Bit 31 is sign bit
n 1 for negative numbers
n 0 for non-negative numbers
n –(–2
n – 1
) can’t be represented
n Non-negative numbers have the same unsigned
and 2s-complement representation
n Some specific numbers
n 0: 0000 0000 … 0000
n –1: 1111 1111 … 1111
n Most-negative: 1000 0000 … 0000
n Most-positive: 0111 1111 … 1111
Chapter 2 — Instructions: Language of the Computer — 16
Signed Negation
n Complement and add 1
n Complement means 1 → 0, 0 → 1
x1x
11111...111xx
2
-=+
-==+
n Example: negate +2
n +2 = 0000 0000 … 0010
two
n –2 = 1111 1111 … 1101
two
+ 1
= 1111 1111 … 1110
two
Chapter 2 — Instructions: Language of the Computer — 17
Sign Extension
n Representing a number using more bits
n Preserve the numeric value
n Replicate the sign bit to the left
n c.f. unsigned values: extend with 0s
n Examples: 8-bit to 16-bit
n +2: 0000 0010 => 0000 0000 0000 0010
n –2: 1111 1110 => 1111 1111 1111 1110
n In LEGv8 instruction set
n LDURSB: sign-extend loaded byte
n LDURB: zero-extend loaded byte
Chapter 2 — Instructions: Language of the Computer — 18
Representing Instructions
n Instructions are encoded in binary
n Called machine code
n LEGv8 instructions
n Encoded as 32-bit instruction words
n Small number of formats encoding operation code
(opcode), register numbers, …
n Regularity!
§2.5 Representing Instructions in the Computer
Chapter 2 — Instructions: Language of the Computer — 19
Hexadecimal
n Base 16
n Compact representation of bit strings
n 4 bits per hex digit
0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111
n Example: eca8 6420
n 1110 1100 1010 1000 0110 0100 0010 0000
Chapter 2 — Instructions: Language of the Computer — 20
LEGv8 R-format Instructions
n Instruction fields
n opcode: operation code
n Rm: the second register source operand
n shamt: shift amount (00000 for now)
n Rn: the first register source operand
n Rd: the register destination
opcode Rm shamt Rn Rd
11 bits 5 bits 6 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 21
R-format Example
ADD X9,X20,X21
1112
ten
21
ten
0
ten
20
ten
9
ten
10001011000
two
10101
two
000000
two
10100
two
01001
two
1000 1011 0001 0101 0000 0010 1000 1001
two
=
8B150289
16
opcode Rm shamt Rn Rd
11 bits 5 bits 6 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 22
LEGv8 D-format Instructions
n Load/store instructions
n Rn: base register
n address: constant offset from contents of base register (+/- 32
doublewords)
n Rt: destination (load) or source (store) register number
n Design Principle 3: Good design demands good
compromises
n Different formats complicate decoding, but allow 32-bit
instructions uniformly
n Keep formats as similar as possible
opcode op2 Rn Rt
11 bits 9 bits 2 bits 5 bits 5 bits
address
Chapter 2 — Instructions: Language of the Computer — 23
LEGv8 I-format Instructions
n Immediate instructions
n Rn: source register
n Rd: destination register
n Immediate field is zero-extended
opcode Rn Rd
10 bits 12 bits 5 bits 5 bits
immediate
Chapter 2 — Instructions: Language of the Computer — 24
Stored Program Computers
n Instructions represented in
binary, just like data
n Instructions and data stored
in memory
n Programs can operate on
programs
n e.g., compilers, linkers, …
n Binary compatibility allows
compiled programs to work
on different computers
n Standardized ISAs
The BIG Picture
Chapter 2 — Instructions: Language of the Computer — 25
Logical Operations
n Instructions for bitwise manipulation
Operation C/Java Java
(unsigned)
LEGv8
Shift left << <<<
LSL
Shift right >> >>>
LSR
Bit-by-bit AND & &
AND, ANDI
Bit-by-bit OR | |
OR, ORI
Bit-by-bit NOT ~ ~
EOR, EORI
n Useful for extracting and inserting
groups of bits in a word
§2.6 Logical Operations
Chapter 2 — Instructions: Language of the Computer — 26
Shift Operations
n shamt: how many positions to shift
n Shift left logical
n Shift left and fill with 0 bits
n LSL by i bits multiplies by 2
i
n Shift right logical
n Shift right and fill with 0 bits
n LSR by i bits divides by 2
i
(unsigned only)
opcode Rm shamt Rn Rd
11 bits 5 bits 6 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 27
AND Operations
n Useful to mask bits in a word
n Select some bits, clear others to 0
AND X9,X10,X11
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
X10
X11
X9
00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000
Chapter 2 — Instructions: Language of the Computer — 28
OR Operations
n Useful to include bits in a word
n Set some bits to 1, leave others unchanged
OR X9,X10,X11
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
X10
X11
X9
00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000
Chapter 2 — Instructions: Language of the Computer — 29
EOR Operations
n Differencing operation
n Set some bits to 1, leave others unchanged
EOR X9,X10,X12 // NOT operation
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
X10
X12
X9
11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111
11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111
Chapter 2 — Instructions: Language of the Computer — 30
Conditional Operations
n Branch to a labeled instruction if a condition is
true
n Otherwise, continue sequentially
n CBZ register, L1
n if (register == 0) branch to instruction labeled L1;
n CBNZ register, L1
n if (register != 0) branch to instruction labeled L1;
n B L1
n branch unconditionally to instruction labeled L1;
§2.7 Instructions for Making Decisions
Chapter 2 — Instructions: Language of the Computer — 31
Compiling If Statements
n C code:
if (i==j) f = g+h;
else f = g-h;
n f, g, … in X19, X20, …
n Compiled LEGv8 code:
SUB X9,X22,X23
CBNZ X9,Else
ADD X19,X20,X21
B Exit
Else: SUB X19,X20,x21
Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 32
Compiling Loop Statements
n C code:
while (save[i] == k) i += 1;
n i in X22, k in X24, address of save in x25
n Compiled LEGv8 code:
Loop: LSL X10, X22,#3
ADD X10, X10, X25
LDUR X9,[X10,#0]
SUB X11, X9, X24
CBNZ X11,Exit
ADDI X22, X22,#1
B Loop
Exit: …
Chapter 2 — Instructions: Language of the Computer — 33
Basic Blocks
n A basic block is a sequence of instructions
with
n No embedded branches (except at end)
n No branch targets (except at beginning)
n A compiler identifies basic
blocks for optimization
n An advanced processor
can accelerate execution
of basic blocks
Chapter 2 — Instructions: Language of the Computer — 34
More Conditional Operations
n Condition codes, set from arithmetic instruction with S-
suffix (ADDS, ADDIS, ANDS, ANDIS, SUBS, SUBIS)
n negative (N): result had 1 in MSB
n zero (Z): result was 0
n overlow (V): result overflowed
n carry (C): result had carryout from MSB
n Use subtract to set flags, then conditionally branch:
n B.EQ
n B.NE
n B.LT (less than, signed), B.LO (less than, unsigned)
n B.LE (less than or equal, signed), B.LS (less than or equal, unsigned)
n B.GT (greater than, signed), B.HI (greater than, unsigned)
n B.GE (greater than or equal, signed),
n B.HS (greater than or equal, unsigned)
Conditional Example
n if (a > b) a += 1;
n a in X22, b in X23
SUBS X9,X22,X23 // use subtract to make comparison
B.LTE Exit // conditional branch
ADDI X22,X22,#1
Exit:
Chapter 2 — Instructions: Language of the Computer — 35
Chapter 2 — Instructions: Language of the Computer — 36
Signed vs. Unsigned
n Signed comparison
n Unsigned comparison
n Example
n X22 = 1111 1111 1111 1111 1111 1111 1111 1111
n X23 = 0000 0000 0000 0000 0000 0000 0000 0001
n X22 < X23 # signed
n –1 < +1
n X22 > X23 # unsigned
n +4,294,967,295 > +1
Chapter 2 — Instructions: Language of the Computer — 37
Procedure Calling
n Steps required
1. Place parameters in registers X0 to X7
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call (address in X30)
§2.8 Supporting Procedures in Computer Hardware
Chapter 2 — Instructions: Language of the Computer — 38
Procedure Call Instructions
n Procedure call: jump and link
BL ProcedureLabel
n Address of following instruction put in X30
n Jumps to target address
n Procedure return: jump register
BR LR
n Copies LR to program counter
n Can also be used for computed jumps
n e.g., for case/switch statements
Chapter 2 — Instructions: Language of the Computer — 39
Leaf Procedure Example
n C code:
long long int leaf_example (long long int
g, long long int h, long long int i, long
long int j)
{ long long int f;
f = (g + h) - (i + j);
return f;
}
n Arguments g, …, j in X0, …, X3
n f in X19 (hence, need to save X19 on stack)
n LEGv8 code:
leaf_example:
SUBI SP,SP,#24
STUR X10,[SP,#16]
STUR X9,[SP,#8]
STUR X19,[SP,#0]
ADD X9,X0,X1
ADD X10,X2,X3
SUB X19,X9,X10
ADD X0,X19,XZR
LDUR X10,[SP,#16]
LDUR X9,[SP,#8]
LDUR X19,[SP,#0]
ADDI SP,SP,#24
BR LR
Chapter 2 — Instructions: Language of the Computer — 40
Leaf Procedure Example
Save X10, X9, X19 on stack
X9 = g + h
X10 = i + j
f = X9 – X10
copy f to return register
Restore X10, X9, X19 from stack
Return to caller
Notes
n X9–X17
n temporary registers that are not preserved by
the callee (called procedure) on a procedure
call
n X19–X28: saved registers that must be
preserved on a procedure call
n if used, the calle e saves and restores them
Chapter 2 — Instructions: Language of the Computer — 41
Local Data on the Stack
Chapter 2 — Instructions: Language of the Computer — 42
Register Usage in Subroutines
n X9 to X17: temporary registers
n Not preserved by the callee
n X19 to X28: saved registers
n If used, the callee saves and restores them
Chapter 2 — Instructions: Language of the Computer — 43
Chapter 2 — Instructions: Language of the Computer — 44
Non-Leaf Procedures
n Procedures that call other procedures
n For nested call, caller needs to save on the
stack:
n Its return address
n Any arguments and temporaries needed after
the call
n Restore from the stack after the call
Chapter 2 — Instructions: Language of the Computer — 45
Non-Leaf Procedure Example
n C code:
int fact (int n)
{
if (n < 1) return 1;
else return n * fact(n - 1);
}
n Argument n in X0
n Result in X1
n LEGv8 code:
fact:
SUBI SP,SP,#16
STUR LR,[SP,#8]
STUR X0,[SP,#0]
SUBIS XZR,X0,#1
B.GE L1
ADDI X1,XZR,#1
ADDI SP,SP,#16
BR LR
L1: SUBI X0,X0,#1
BL fact
LDUR X0,[SP,#0]
LDUR LR,[SP,#8]
ADDI SP,SP,#16
MUL X1,X0,X1
BR LR
Chapter 2 — Instructions: Language of the Computer — 46
Non-Leaf Procedure Example
Save return address and n on stack
compare n and 1
Else, set return value to 1
n = n - 1
if n >= 1, go to L1
call fact(n-1)
Pop stack, don’t bother restoring values
Return
Restore caller’s n
Restore caller’s return address
Pop stack
return n * fact(n-1)
return
Chapter 2 — Instructions: Language of the Computer — 47
Memory Layout
n Text: program code
n Static data: global
variables
n e.g., static variables in C,
constant arrays and strings
n Dynamic data: heap
n E.g., malloc in C, new in
Java
n Stack: automatic storage
Chapter 2 — Instructions: Language of the Computer — 48
Character Data
n Byte-encoded character sets
n ASCII: 128 characters
n 95 graphic, 33 control
n Latin-1: 256 characters
n ASCII, +96 more graphic characters
n Unicode: 32-bit character set
n Used in Java, C++ wide characters, …
n Most of the world’s alphabets, plus symbols
n UTF-8, UTF-16: variable-length encodings
§2.9 Communicating with People
Chapter 2 — Instructions: Language of the Computer — 49
Byte/Halfword Operations
n LEGv8 byte/halfword load/store
n Load byte:
n LDURB Rt, [Rn, offset]
n Sign extend to 32 bits in rt
n Store byte:
n STURB Rt, [Rn, offset]
n Store just rightmost byte
n Load halfword:
n LDURH Rt, [Rn, offset]
n Sign extend to 32 bits in rt
n Store halfword:
n STURH Rt, [Rn, offset]
n Store just rightmost halfword
Chapter 2 — Instructions: Language of the Computer — 50
String Copy Example
n C code:
n Null-terminated string
void strcpy (char x[], char y[])
{ size_t i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
n LEGv8 code:
strcpy:
SUBI SP,SP,8 // push X19
STUR X19,[SP,#0]
ADD X19,XZR,XZR // i=0
L1: ADD X10,X19,X1 // X10 = addr of y[i]
LDURB X11,[X10,#0] // X11 = y[i]
ADD X12,X19,X0 // X12 = addr of x[i]
STURB X11,[X12,#0] // x[i] = y[i]
CBZ X11,L2 // if y[i] == 0 then exit
ADDI X19,X19,#1 // i = i + 1
B L1 // next iteration of loop
L2: LDUR X19,[SP,#0] // restore saved $s0
ADDI SP,SP,8 // pop 1 item from stack
BR LR // and return
Chapter 2 — Instructions: Language of the Computer — 51
String Copy Example
n Most constants are small
n 12-bit immediate is sufficient
n For the occasional 32-bit constant
MOVZ: move wide with zeros
MOVK: move with with keep
n Use with flexible second operand (shift)
Chapter 2 — Instructions: Language of the Computer — 52
0000 0000 0000 0000
32-bit Constants
MOVZ X9,255,LSL 16
§2.10 LEGv8 Addressing for 32-Bit Immediates and Addresses
MOVK X9,255,LSL 0
0000 0000 0000 0000
0000 0000 1111 1111 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 1111 1111
Branch Addressing
n B-type
n B 1000 // go to location 10000
ten
n CB-type
n CBNZ X19, Exit // go to Exit if X19 != 0
n Both addresses are PC-relative
n Address = PC + offset (from instruction)
Chapter 2 — Instructions: Language of the Computer — 53
5 10000
ten
6 bits 26 bits
181 Exit
8 bits 19 bits
19
5 bits
LEGv8 Addressing Summary
Chapter 2 — Instructions: Language of the Computer — 54
LEGv8 Encoding Summary
Chapter 2 — Instructions: Language of the Computer — 55
Chapter 2 — Instructions: Language of the Computer — 56
Synchronization
n Two processors sharing an area of memory
n P1 writes, then P2 reads
n Data race if P1 and P2 don’t synchronize
n Result depends of order of accesses
n Hardware support required
n Atomic read/write memory operation
n No other access to the location allowed between the
read and write
n Could be a single instruction
n E.g., atomic swap of register ↔ memory
n Or an atomic pair of instructions
§2.11 Parallelism and Instructions: Synchronization
Chapter 2 — Instructions: Language of the Computer — 57
Synchronization in LEGv8
n Load exclusive register: LDXR
n Store exclusive register: STXR
n To use:
n Execute LDXR then STXR with same address
n If there is an intervening change to the address, store
fails (communicated with additional output register)
n Only use register instruction in between
Synchronization in LEGv8
n Example 1: atomic swap (to test/set lock variable)
again: LDXR X10,[X20,#0]
STXR X23,X9,[X20] // X9 = status
CBNZ X9, again
ADD X23,XZR,X10 // X23 = loaded value
n Example 2: lock
ADDI X11,XZR,#1 // copy locked value
again: LDXR X10,[X20,#0] // read lock
CBNZ X10, again // check if it is 0 yet
STXR X11, X9, [X20] // attempt to store
BNEZ X9,again // branch if fails
n Unlock:
STUR XZR, [X20,#0] // free lock
Chapter 2 — Instructions: Language of the Computer — 58
Chapter 2 — Instructions: Language of the Computer — 59
Translation and Startup
Many compilers produce
object modules directly
Static linking
§2.12 Translating and Starting a Program
Chapter 2 — Instructions: Language of the Computer — 60
Producing an Object Module
n Assembler (or compiler) translates program into
machine instructions
n Provides information for building a complete
program from the pieces
n Header: described contents of object module
n Text segment: translated instructions
n Static data segment: data allocated for the life of the
program
n Relocation info: for contents that depend on absolute
location of loaded program
n Symbol table: global definitions and external refs
n Debug info: for associating with source code
Chapter 2 — Instructions: Language of the Computer — 61
Linking Object Modules
n Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3. Patch location-dependent and external refs
n Could leave location dependencies for
fixing by a relocating loader
n But with virtual memory, no need to do this
n Program can be loaded into absolute location
in virtual memory space
Chapter 2 — Instructions: Language of the Computer — 62
Loading a Program
n Load from image file on disk into memory
1. Read header to determine segment sizes
2. Create virtual address space
3. Copy text and initialized data into memory
n Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including SP, FP)
6. Jump to startup routine
n Copies arguments to X0, … and calls main
n When main returns, do exit syscall
Chapter 2 — Instructions: Language of the Computer — 63
Dynamic Linking
n Only link/load library procedure when it is
called
n Requires procedure code to be relocatable
n Avoids image bloat caused by static linking of
all (transitively) referenced libraries
n Automatically picks up new library versions
Chapter 2 — Instructions: Language of the Computer — 64
Lazy Linkage
Indirection table
Stub: Loads routine ID,
Jump to linker/loader
Linker/loader code
Dynamically
mapped code
Chapter 2 — Instructions: Language of the Computer — 65
Starting Java Applications
Simple portable
instruction set for
the JVM
Interprets
bytecodes
Compiles
bytecodes of
“hot” methods
into native
code for host
machine
Chapter 2 — Instructions: Language of the Computer — 66
C Sort Example
n Illustrates use of assembly instructions
for a C bubble sort function
n Swap procedure (leaf)
void swap(long long int v[],
long long int k)
{
long long int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
n v in X0, k in X1, temp in X9
§2.13 A C Sort Example to Put It All Together
swap: LSL X10,X1,#3 // X10 = k * 8
ADD X10,X0,X10 // X10 = address of v[k]
LDUR X9,[X10,#0] // X9 = v[k]
LDUR X11,[X10,#8] // X11 = v[k+1]
STUR X11,[X10,#0] // v[k] = X11 (v[k+1])
STUR X9,[X10,#8] // v[k+1] = X9 (v[k])
BR LR // return to calling routine
Chapter 2 — Instructions: Language of the Computer — 67
The Procedure Swap
Chapter 2 — Instructions: Language of the Computer — 68
The Sort Procedure in C
n Non-leaf (calls swap)
void sort (long long int v[], size_t n)
{
size_t i, j;
for (i = 0; i < n; i += 1) {
for (j = i – 1;
j >= 0 && v[j] > v[j + 1];
j -= 1) {
swap(v,j);
}
}
}
n v in X0, n in X1, i in X19, j in X20
n Skeleton of outer loop:
n for (i = 0; i <n; i += 1) {
MOV X19,XZR // i = 0
for1tst:
CMP X19, X1 // compare X19 to X1 (i to n)
B.GE exit1 // go to exit1 if X19 ≥ X1 (i≥n)
(body of outer for-loop)
ADDI X19,X19,#1 // i += 1
B for1tst // branch to test of outer loop
exit1:
Chapter 2 — Instructions: Language of the Computer — 69
The Outer Loop
n Skeleton of inner loop:
n for (j = i − 1; j >= 0 && v[j] > v[j + 1]; j − = 1) {
SUBI X20, X19, #1 // j = i - 1
for2tst: CMP X20,XZR // compare X20 to 0 (j to 0)
B.LT exit2 // go to exit2 if X20 < 0 (j < 0)
LSL X10, X20, #3 // reg X10 = j * 8
ADD X11, X0, X10 // reg X11 = v + (j * 8)
LDUR X12, [X11,#0] // reg X12 = v[j]
LDUR X13, [X11,#8] // reg X13 = v[j + 1]
CMP X12, X13 // compare X12 to X13
B.LE exit2 // go to exit2 if X12 ≤ X13
MOV X0, X21 // first swap parameter is v
MOV X1, X20 // second swap parameter is j
BL swap // call swap
SUBI X20, X20, #1 // j –= 1
B for2tst // branch to test of inner loop
exit2:
Chapter 2 — Instructions: Language of the Computer — 70
The Inner Loop
n Preserve saved registers:
SUBI SP,SP,#40 // make room on stack for 5 regs
STUR LR,[SP,#32] // save LR on stack
STUR X22,[SP,#24] // save X22 on stack
STUR X21,[SP,#16] // save X21 on stack
STUR X20,[SP,#8] // save X20 on stack
STUR X19,[SP,#0] // save X19 on stack
MOV X21, X0 // copy parameter X0 into X21
MOV X22, X1 // copy parameter X1 into X22
n Restore saved registers:
exit1: LDUR X19, [SP,#0] // restore X19 from stack
LDUR X20, [SP,#8] // restore X20 from stack
LDUR X21,[SP,#16] // restore X21 from stack
LDUR X22,[SP,#24] // restore X22 from stack
LDUR X30,[SP,#32] // restore LR from stack
SUBI SP,SP,#40 // restore stack pointer
Chapter 2 — Instructions: Language of the Computer — 71
Preserving Registers
Chapter 2 — Instructions: Language of the Computer — 72
Effect of Compiler Optimization
0
0.5
1
1.5
2
2.5
3
none O1 O2 O3
Relative Performance
0
20000
40000
60000
80000
100000
120000
140000
160000
180000
none O1 O2 O3
Clock Cycles
0
20000
40000
60000
80000
100000
120000
140000
none O1 O2 O3
Instruction count
0
0.5
1
1.5
2
none O1 O2 O3
CPI
Compiled with gcc for Pentium 4 under Linux
Chapter 2 — Instructions: Language of the Computer — 73
Effect of Language and Algorithm
0
0.5
1
1.5
2
2.5
3
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Bubblesort Relative Performance
0
0.5
1
1.5
2
2.5
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Quicksort Relative Performance
0
500
1000
1500
2000
2500
3000
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Quicksort vs. Bubblesort Speedup
Chapter 2 — Instructions: Language of the Computer — 74
Lessons Learnt
n Instruction count and CPI are not good
performance indicators in isolation
n Compiler optimizations are sensitive to the
algorithm
n Java/JIT compiled code is significantly
faster than JVM interpreted
n Comparable to optimized C in some cases
n Nothing can fix a dumb algorithm!
Chapter 2 — Instructions: Language of the Computer — 75
Arrays vs. Pointers
n Array indexing involves
n Multiplying index by element size
n Adding to array base address
n Pointers correspond directly to memory
addresses
n Can avoid indexing complexity
§2.14 Arrays versus Pointers
Chapter 2 — Instructions: Language of the Computer — 76
Example: Clearing an Array
clear1(int array[], int size) {
int i;
for (i = 0; i < size; i += 1)
array[i] = 0;
}
clear2(int *array, int size) {
int *p;
for (p = &array[0]; p < &array[size];
p = p + 1)
*p = 0;
}
MOV X9,XZR // i = 0
loop1: LSL X10,X9,#3 // X10 = i * 8
ADD X11,X0,X10 // X11 = address
// of array[i]
STUR XZR,[X11,#0]
// array[i] = 0
ADDI X9,X9,#1 // i = i + 1
CMP X9,X1 // compare i to
// size
B.LT loop1 // if (i < size)
// go to loop1
MOV X9,X0 // p = address of
// array[0]
LSL X10,X1,#3 // X10 = size * 8
ADD X11,X0,X10 // X11 = address
// of array[size]
loop2: STUR XZR,0[X9,#0]
// Memory[p] = 0
ADDI X9,X9,#8 // p = p + 8
CMP X9,X11 // compare p to <
// &array[size]
B.LT loop2 // if (p <
// &array[size])
// go to loop2
Chapter 2 — Instructions: Language of the Computer — 77
Comparison of Array vs. Ptr
n Multiply “strength reduced” to shift
n Array version requires shift to be inside
loop
n Part of index calculation for incremented i
n c.f. incrementing pointer
n Compiler can achieve same effect as
manual use of pointers
n Induction variable elimination
n Better to make program clearer and safer
Chapter 2 — Instructions: Language of the Computer — 78
ARM & MIPS Similarities
n ARM: the most popular embedded core
n Similar basic set of instructions to MIPS
§2.16 Real Stuff: ARM Instructions
ARM MIPS
Date announced 1985 1985
Instruction size 32 bits 32 bits
Address space 32-bit flat 32-bit flat
Data alignment Aligned Aligned
Data addressing modes 9 3
Registers 15 × 32-bit 31 × 32-bit
Input/output Memory
mapped
Memory
mapped
Chapter 2 — Instructions: Language of the Computer — 79
Instruction Encoding
Chapter 2 — Instructions: Language of the Computer — 80
The Intel x86 ISA
n Evolution with backward compatibility
n 8080 (1974): 8-bit microprocessor
n Accumulator, plus 3 index-register pairs
n 8086 (1978): 16-bit extension to 8080
n Complex instruction set (CISC)
n 8087 (1980): floating-point coprocessor
n Adds FP instructions and register stack
n 80286 (1982): 24-bit addresses, MMU
n Segmented memory mapping and protection
n 80386 (1985): 32-bit extension (now IA-32)
n Additional addressing modes and operations
n Paged memory mapping as well as segments
§2.17 Real Stuff: x86 Instructions
Chapter 2 — Instructions: Language of the Computer — 81
The Intel x86 ISA
n Further evolution…
n i486 (1989): pipelined, on-chip caches and FPU
n Compatible competitors: AMD, Cyrix, …
n Pentium (1993): superscalar, 64-bit datapath
n Later versions added MMX (Multi-Media eXtension)
instructions
n The infamous FDIV bug
n Pentium Pro (1995), Pentium II (1997)
n New microarchitecture (see Colwell, The Pentium Chronicles)
n Pentium III (1999)
n Added SSE (Streaming SIMD Extensions) and associated
registers
n Pentium 4 (2001)
n New microarchitecture
n Added SSE2 instructions
Chapter 2 — Instructions: Language of the Computer — 82
The Intel x86 ISA
n And further…
n AMD64 (2003): extended architecture to 64 bits
n EM64T – Extended Memory 64 Technology (2004)
n AMD64 adopted by Intel (with refinements)
n Added SSE3 instructions
n Intel Core (2006)
n Added SSE4 instructions, virtual machine support
n AMD64 (announced 2007): SSE5 instructions
n Intel declined to follow, instead…
n Advanced Vector Extension (announced 2008)
n Longer SSE registers, more instructions
n If Intel didn’t extend with compatibility, its
competitors would!
n Technical elegance ≠ market success
Chapter 2 — Instructions: Language of the Computer — 83
Basic x86 Registers
Chapter 2 — Instructions: Language of the Computer — 84
Basic x86 Addressing Modes
n Two operands per instruction
Source/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate
n Memory addressing modes
n Address in register
n Address = R
base
+ displacement
n Address = R
base
+ 2
scale
× R
index
(scale = 0, 1, 2, or 3)
n Address = R
base
+ 2
scale
× R
index
+ displacement
Chapter 2 — Instructions: Language of the Computer — 85
x86 Instruction Encoding
n Variable length
encoding
n Postfix bytes specify
addressing mode
n Prefix bytes modify
operation
n Operand length,
repetition, locking, …
Chapter 2 — Instructions: Language of the Computer — 86
Implementing IA-32
n Complex instruction set makes
implementation difficult
n Hardware translates instructions to simpler
microoperations
n Simple instructions: 1–1
n Complex instructions: 1–many
n Microengine similar to RISC
n Market share makes this economically viable
n Comparable performance to RISC
n Compilers avoid complex instructions
Chapter 2 — Instructions: Language of the Computer — 87
Fallacies
n Powerful instruction Þ higher performance
n Fewer instructions required
n But complex instructions are hard to implement
n May slow down all instructions, including simple ones
n Compilers are good at making fast code from simple
instructions
n Use assembly code for high performance
n But modern compilers are better at dealing with
modern processors
n More lines of code Þ more errors and less
productivity
§2.19 Fallacies and Pitfalls
Chapter 2 — Instructions: Language of the Computer — 88
Fallacies
n Backward compatibility Þ instruction set
doesn’t change
n But they do accrete more instructions
x86 instruction set
Chapter 2 — Instructions: Language of the Computer — 89
Pitfalls
n Sequential words are not at sequential
addresses
n Increment by 4, not by 1!
n Keeping a pointer to an automatic variable
after procedure returns
n e.g., passing pointer back via an argument
n Pointer becomes invalid when stack popped
Chapter 2 — Instructions: Language of the Computer — 90
Concluding Remarks
n Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good compromises
n Layers of software/hardware
n Compiler, assembler, hardware
n LEGv8: typical of RISC ISAs
n c.f. x86
§2.20 Concluding Remarks
Chapter 2 — Instructions: Language of the Computer — 91
Concluding Remarks
n Additional ARMv8 features:
n Flexible second operand
n Additional addressing modes
n Conditional instructions (e.g. CSET, CINC)
